1. Technical Field
Example embodiments relate to a deskew technique between data signals and clock, and more particularly, to a deskew system for eliminating skew between received data signals and clock, and circuits for the deskew system.
2. Description of Related Art
When serially transmitted data is received as parallel data in a data transmission system, skew is generated between the received data and a clock signal so that an error may be generated in data transmission. To eliminate the skew between the data and clock, a phase difference between data and clock is detected and a detected phase difference is compensated. The phase difference between data and clock is detected in a phase tracking method and a phase picking method.
FIG. 1A illustrates a phase tracking type sampling method. Referring to FIG. 1A, an ideal clock position and a change of a sampling value according to an increase or decrease of clock delay can be seen. According to the phase tracking method, tracking is performed to seek for the position of a desired clock based on a sampled signal.
The phase tracking method has a merit that a sampling method is simple but has a demerit in that sufficient data transition and loop locking time due to feedback are used. Recently, as a data transmission speed is rapidly increased, the phase picking method is mainly used to reduce a loss in data operation speed.
FIG. 1B illustrates a phase picking type sampling method. Referring to FIG. 1B, according to the phase picking method, the position of a desired clock may be determined and selected using the transition of an over-sampled signal. Thus, the phase picking method has a merit of reducing time for synchronization and a loss in data operation speed.
However, the phase picking method has demerits in that a phase delay range of clock for skew compensation is at least half of a cycle and a bit error rate increases when an over-sampling number for data is decreased to reduce the loss of data operation speed.
Also, in the phase picking method, data is sampled several times using a plurality of clocks having different phases and deskew is performed based on an accumulated sampling result. Thus, when the number of clocks for sampling and the frequency of sampling are increased to improve deskew performance, a chip size and power consumption are increased accordingly.